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[VHDL-FPGA-Verilog] ip_fft128

Description: 128点fft的IP核vhdl源代码，另有其控制代码。-128 point fft s IP core VHDL source code, while its control code.
Platform: | Size: 7168 | Author: 戈立军 | Hits:

[VHDL-FPGA-Verilog] pci_express_crc

Description: PCI express CRC rtl core for Fpga/asic Designer
Platform: | Size: 202752 | Author: 李晓媛 | Hits:

[VHDL-FPGA-Verilog] Ethernet_verilog_ip_core

Description: Ethernet(以太网)verilog ip core用verilogHDL语言写的以太网软核，对学习verilog语言和以太网有很大帮助。-Ethernet (Ethernet) verilog ip core language used verilogHDL Ethernet soft-core, learning Verilog language and Ethernet are very helpful.
Platform: | Size: 903168 | Author: houlongting | Hits:

[ARM-PowerPC-ColdFire-MIPS] arm9_fpga2_verilog

Description:
Platform: | Size: 195584 | Author: houlongting | Hits:

[VHDL-FPGA-Verilog] spi_op_core

Description: 串行数据SPI master的开源控制器，verilog，内附说明-SPI master serial data open-source controller, verilog, containing a description
Platform: | Size: 81920 | Author: 王天 | Hits:

[VHDL-FPGA-Verilog] VerilogHDL

Description: 精通VerilogHDL：IC设计核心技术实例详解-Proficient VerilogHDL: IC design Detailed examples of core technology
Platform: | Size: 520192 | Author: JACK | Hits:

[SCM] 8051ipcore

Description: 8051的IP内核，用verilog编写，可以实现8051的一般功能-8051 IP core, prepared using Verilog, you can realize the general function of 8051
Platform: | Size: 52224 | Author: 王天 | Hits:

[VHDL-FPGA-Verilog] Nios

Description: nois 2cpu 硬件实现编程，在fgja上实现软核-nois 2cpu hardware programming, in the realization of soft-core fgja
Platform: | Size: 1173504 | Author: xiaohuaifeng | Hits:

[VHDL-FPGA-Verilog] 8255

Description: Verilog语言描述的Intel8255 IP Core，本人已经在某项目中经过了物理验证的，可直接用于FPGA综合或ASIC综合。
Platform: | Size: 6144 | Author: David.Mr.Liu | Hits:

[Other] EHERNETIPcore

Description: 该文件包含以太网IP核的相关代码，一共包含24个VERILOG源代码-This document contains the relevant Ethernet IP core code, a total of 24 includes Verilog source code
Platform: | Size: 69632 | Author: season | Hits:

[VHDL-FPGA-Verilog] oscilloscope_using_FPGA

Description: verilog编写基于FPGA的示波器核心实现-Verilog FPGA-based oscilloscope to prepare the core of the achievement of
Platform: | Size: 1015808 | Author: 宇天 | Hits:

[VHDL-FPGA-Verilog] ISE_assistant_design_tool

Description: Xilinx－ISE辅助设计工具的中文使用说明，包括IP核生成器，布局布线器，FPGA底层编辑器，时序分析器，集成化逻辑分析工具，功率分析工具-Xilinx-ISE-aided design tools for use in Chinese, including the IP core generator, layout router, FPGA Editor bottom, timing analyzer, integrated logic analysis tools, power analysis tools
Platform: | Size: 1589248 | Author: joan | Hits:

[VHDL-FPGA-Verilog] SRAM_16Bit_512K

Description: Verilog 编写的IP核，512K的16位SRAM-Written in Verilog IP core, 512K 16-bit SRAM
Platform: | Size: 11264 | Author: zhyy | Hits:

[VHDL-FPGA-Verilog] DM9000A

Description: Verilog 编写的网卡DM9000A的IP核，altera公司寄的DE2系统中的源程序核-Verilog prepared DM9000A the IP core network card, altera company sent DE2 System source of nuclear
Platform: | Size: 16384 | Author: zhyy | Hits:

[VHDL-FPGA-Verilog] ISP1362

Description: Verilog 编写的ISP1362的控制器IP核，altera公司DE2系统中的源程序-Verilog prepared ISP1362 controller IP core, altera company source DE2 System
Platform: | Size: 18432 | Author: zhyy | Hits:

[Software Engineering] ps2_ipcore_design

Description: 电子测量技术 ELECTR0NIC MEASI瓜EMENT TECHN0L0GY 第29卷第3期 2006年6月 PS／2设备接口IP核设计 王 豪黄启俊常 胜 (武汉大学物理学院微电子与固体电子学实验室武汉430072) 摘要：用Verilog硬件描述语言实现了PS／2设备接口的II)核设计，详细描述了II)核的结构划分和各模块的 设计思想，并在FPGA上进行验证。结果表明此 核功能正确，可以方便地在SOPC系统中复用。-Electronic Measurement Technology ELECTR0NIC MEASI melon EMENT TECHN0L0GY Vol 29 No. 3 June 2006 PS/2 device interface IP core design黄启俊Changsheng WANG Hao (School of Physics, Wuhan University Microelectronics and Solid State Electronics Laboratory, Wuhan 430072) Abstract: Verilog hardware description language to achieve a PS/2 device interface of II) of nuclear design, described in detail II) the structure of nuclear division and the module
Platform: | Size: 126976 | Author: Morgan | Hits:

[Program doc] ddc

Description: 介绍了一种基于软件无线电思想的频分多址中频数字化接收机系统设计方案。它采用Altera公司的FPGA构成核 心单元,通过不同的软件配置实现对三路频分多址信号的解调。 -Introduce a software-based radio thinking FDMA digital IF receiver system design. It uses Altera s FPGA constitute the core unit, through different software configuration for the three-way realize FDMA signal demodulation.
Platform: | Size: 816128 | Author: 可难 | Hits:

[VHDL-FPGA-Verilog] FPGAdezizhixingSPWMboChengXu

Description: 基于FPGA的自治型SPWM波形发生器的设计！正弦脉宽调制（SPWM）技术在以电压源逆变电路为核心的电力电子装置中有着广泛的应用，如何产生SPWM脉冲序列及其实现手段是PWM技术的关键。大家共同探讨哈！-FPGA based SPWM autonomy-based waveform generator design! Sinusoidal pulse width modulation (SPWM) technology in the voltage source inverter circuit as the core of the power electronic devices have a wide range of applications, how to generate SPWM pulse sequence and its implementation means PWM technology is the key. Kazakhstan investigate everyone!
Platform: | Size: 4096 | Author: 小喻 | Hits:

[VHDL-FPGA-Verilog] fpgaPCI

Description: fpga开发pci的verilog，不可多得的源代码。-FPGA development pci of verilog, rare source code.
Platform: | Size: 1726464 | Author: 王军 | Hits:

[VHDL-FPGA-Verilog] PWM

Description: 使用VERILOG 语言产生PWM波。只需要使用处理器或内核直接配置相应的寄存器就可以输出PWM波。-VERILOG language use PWM wave generated. Only need to use the processor or core directly corresponding configuration register can output PWM wave.
Platform: | Size: 2048 | Author: 望习才 | Hits:
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